Presently known digital-to-analog converters ("DACs" or "D/A converters") for use in digital audio systems are configured to perform a variety of signal processing functions. For example, the CMOS LSI .SIGMA.DECO SM5871AS digital audio D/A converter manufactured by Nippon Precision Circuits Ltd. ("NPC") inputs digital data from a compact disc at a predetermined sample frequency Fs, and processes the data using the following functional modules: an infinite impulse response ("IIR") de-emphasis filter; a digital attenuator; an 8.times. oversampling filter; a sigma-delta (.DELTA.-.SIGMA.) modulator (noise shaper); and a pulse width modulator (PWM). The pulse width modulated output of the D/A converter may-then be low-pass filtered, amplified and applied to a conventional audio speaker to generate sound reproduction of the digital data. The three 2.times. interpolation stages may be selectively configured as a single stage (2.times.), a two stage (2.times.2.times.)=4.times., or a three stage (2.times.2.times.2.times.)=8.times. oversampling digital filter, to ultimately effect a desired degree of interpolation (oversampling) of the input data. For an 8.times. interpolating filter, the interpolated data is applied to the .DELTA.-.SIGMA. modulator at a frequency of 8 Fs.
In the NPC D/A converter, the .DELTA.-.SIGMA. modulator functionally comprises an initial sample and hold module, followed by a noise shaping module. Such sample and hold modules typically effect additional oversampling, for example 4.times. interpolation. The resulting output from the .DELTA.-.SIGMA. modulator comprises a 32.times. interpolation of the original input data at a frequency of 32 Fs. The noise shaping module is configured to effectively shift the quantization noise introduced in the .DELTA.-.SIGMA. modulation into high frequency regions beyond the audible range. The output of the noise shaping module is applied to a pulse width modulator and low-pass filter to produce an analog signal, which is thereafter ultimately applied to an audio transducer to generate sound reproduction of the input data.
In many audio applications, it is common to either simultaneously or sequentially process two or more channels of data (e.g., left and right channel data) for simultaneous reproduction at an audio transducer. That is, a single input data word, for example a left channel data word, may have a corresponding right channel data word associated therewith. For clarity and to facilitate this discussion, the processing of a single data word will be described, it being understood that one or more additional data words (corresponding to additional channels) may also be concomitantly processed for each data word discussed herein.
The processing of digital data in the context of audio systems typically involves sequentially retrieving data words from a data storage location, for example from Read Only Memory (ROM) such as a compact disc (CD). In the context of digital audio reproduction, the well-known Nyquist theorem teaches selecting an input data sample rate which is at least twice the frequency of the highest frequency audible tones. Thus, digital data corresponding to audio signals is typically stored in ROM, in 2's complement format, at a predetermined input sample rate, typically 32.0, 44.1, or 48.0 kHz. As a result of the application of the Nyquist theorem in the context of the compact disc industry wherein the upper range of audible frequencies is generally about 20 kHz, a 44.1 kHz input sample rate (Fs) has emerged as the industry standard.
Presently known CD digital audio play-back systems are often configured to operate at conventional sample rates, for example 44.1 kHz. That is, a single data point is retrieved from ROM during each sample period, each sample period having a duration of 1/44.1 kHz=22.7 microseconds. During each sample period, one complete processing sequence is executed.
The processing of data within a typical D/A converter is governed by a system clock associated with and generally resident within the D/A converter. All aspects of data flow and data manipulation within the converter are typically controlled and synchronized by this system clock. The inputting of input data words from ROM into the D/A converter, on the other hand, is typically controlled by a word clock which is typically not resident on the D/A converter device; rather, the word clock is generally resident in the CD player data retrieved (read head) circuitry.
The word clock generally controls and synchronizes the retrieval of data from CD ROM and the transmission of the input data to the D/A converter. More particularly, the word clock governs the application of input data to an input data interface associated with typical D/A converters. While the period of the system processing (sampling) cycle established by the system clock and the data retrieval period, i.e., the period of the word clock, are ideally coincident, variations between the period of the system processing (sampling) cycle and the period of the word clock are often encountered. These variations (sometimes referred to as "jitter") may become excessive when accumulated over time, causing the word clock to creep with respect to the system cycle, resulting in the disruption of input data flow into the processing modules. Specifically, if the word clock exhibits a period greater than the period of the system cycle, it is possible that the D/A converter may be "ready" to begin processing the next input data word before that input data word has been acquired at the input data interface. Conversely, if the word clock exhibits a period of shorter duration than the period of the system clock, it is possible for an input data word to arrive at the input data interface at a faster rate than the input can be processed in accordance with the (slower) system cycle. In either case, the flow of data is disrupted. Moreover, excessive jitter can degrade the fidelity of the reproduced audio signal.
The processing of digital audio data typically involves a technique known as filtering, Wherein input data is sampled at a sampling frequency Fs, and thereafter interpolated to produce oversampled data at a frequency which is an integer multiple of Fs.
More particularly, a 2.times. interpolation filter typically calculates the value of a new data point midway between each sampled (input) data point, resulting in a stream of data points at a frequency of 2 Fs. One well known technique for performing such interpolation involves multiplying a plurality of input data words by respective predetermined coefficients, and summing the series of products to produce a single interpolated value. The number of data points/coefficients employed in the multiplication/summation operation is referred to as the number of "taps" employed in the filter. Generally, the number of taps within a particular filter stage is proportional to the accuracy with which the magnitude of an interpolated data point may be determined; a larger number of taps yields a more accurate interpolated value. The existence of powerful and mature optimization techniques for determining the value ("weight") of each coefficient permits such filters to be tuned to a high degree of precision.
For an nX interpolation filter, where "n" is any positive integer, a total of n output data points are produced for each input data point. Computational complexity may be reduced by selecting n=2.sup.p, where "p" is any positive integer, such that n=2, 4, 8, etc. In this way, any filter may be implemented as a succession of 2.times. stages; for example, an 8.times. filter may be implemented as a succession of three 2.times. filters, where the output of the first stage 2.times. filter is used as the input for the second stage 2.times. filter, and the output of the second stage filter comprises the input for the third stage 2.times. filter. Such a multi-staged filter is advantageous in that a single stage implementation (e.g., 8.times.) requires a filter of substantially higher order than a multistage filter (e.g., 2.times.2.times.2.times.) effecting the same interpolation.
Computational complexity may also be reduced by employing a symmetrical half band filter, i.e., a filter having an impulse response characteristic which is symmetric about Fs/4. In a symmetrical half band filter nearly one-half of its impulse responses are zero valued (one-half minus one of the taps (every other tap) have a zero valued coefficient and a zero valued data point, and one of the taps has a value of unity), thereby eliminating the need for approximately one-half the number of multiplications for a filter having a given number of taps. Moreover, selecting the coefficient values to be symmetric about the interpolated data point permits two symmetrically disposed data points to be added together and thereafter multiplied by a single coefficient, further reducing the total number of unique non-zero coefficients to t/4 for a filter having "t" taps.
For example, a conventional 2.times. interpolation filter may comprise a total of, e.g., seventy-five (75) taps. For a symmetrical half band filter, thirty-six of these taps have a coefficient value of zero and one has a coefficient value of unity (one). The remaining thirty-eight taps are symmetrically disposed about the interpolated value; hence, only 19 unique non-zero coefficients are required to perform the seventy-five tap interpolation. 2.times. interpolation filters may be cascaded to effect, for example, 4.times., 8.times., and higher resolution interpolation, as desired.
In the context of the aforementioned NPC device, 8.times. interpolated data is further processed (oversampled) by a 4.times. sample and hold module resulting in, for example, 32.times. oversampled data at a frequency of 32 Fs. More particularly, input data is typically retrieved from ROM in words of a predetermined length, typically 16-, 18- or 20-bit format at a frequency of Fs. The 8.times. interpolated data enters the sample and hold module in units of 16- to 20-bit format at 8 Fs. The 16- to 20-bit 4.times. oversampled data from the sample and hold module (resulting in a total of 32.times. oversampling) is applied to the .DELTA.-.SIGMA. modulator at 32 Fs. The .DELTA.-.SIGMA. modulator requantizes the data and outputs the data in a 4-bit format at 32 Fs. Thus, the sample and hold circuit and .DELTA.-.SIGMA. modulator cooperate to convert, e.g., 16-bit data at 8 Fs to 4-bit data at 32 Fs. The resulting 32.times. oversampled data thus comprises the original input data from ROM interleaved with 8.times. interpolated data and 4.times. sample and hold data.
Presently known audio filters are disadvantageous in several respects. For example, although the system cycle (internal to the filter) and the word clock (external to the filter) are intended to operate in synchrony, the actual period of the word clock tends to exhibit some degree of jitter with respect to the actual period of the filter system cycle. Excessive jitter often results in reduced quality in the reproduced sound.
Presently known digital filters often employ multiplier-accumulator based filtering schemes which utilize a hardware multiplier to multiply the various data points by their corresponding filter coefficients. Some systems may also employ a separate multiplier for each channel; the use of dual multipliers permits parallel processing of left and right channel data. While multiplier-accumulator based processing is often more time efficient than shift-and-add processing (i.e., a single multiplication is carried out in few clock cycles), multiplier-accumulator based processing is generally more "real estate" intensive, i.e., occupies a larger region on an integrated circuit, than shift-and-add processing. Thus, the use of multiplier-accumulator based processing may be disadvantageous in circumstances where the physical size of the processing circuitry is a critical design limitation.
A digital audio filter is needed which overcomes the disadvantages of the prior art.